Response of transport triggered architectures for high-speed processor design

This paper reports the result of a comparison between reduced instruction set computing and the transport triggered architecture. Because of the simplicity and efficiency of the transport triggered architecture, its processor requires less execution cycles compared to the OpenRisc processor. This paper also presents a case study about designing an Architecture Definition File for a transport triggered architecture-based design tool, and it depicts how the Architecture Definition File structures are responsible for implementing high-speed design. In a custom Architecture Definition File, a new function unit is designed to improve processor performance, and it shows that the cycle count required to implement the Cyclic Redundancy Check algorithm drops to 7 executions from 5031.